DMA Data Transfer
During a computer's operation it is often necessary for data to be transferred between an external mass storage device, such as a magnetic disk or a magnetic tape, and the internal memory within the computer system. When these types of data transfers are performed by a microprocessor, latency and speed of these transfers are limited by the availability of the microprocessor within the computer and its speed. Using a direct memory access (DMA) technique, it is possible to bypass the microprocessor during such transfers and allow data to be transferred directly between the peripheral device and internal system memory, thus improving speed and reducing latency of the transfer, and correspondingly improving efficiency of the system.
During a DMA transfer, the microprocessor gives up control of the system bus and a DMA controller takes control of the system bus to manage the transfer directly between the peripheral device and the internal system memory. The microprocessor is then free to continue other calculations and operations while the DMA transfer is taking place as long as those other calculations and operations do not require the system bus.
Using a DMA technique, the transfer of data can be made for an entire block of memory words in a single stream of data or the transfer can be made by cycle stealing or transferring one word at a time in between microprocessor instruction executions. During cycle stealing, the microprocessor will delay its operation for one memory cycle to allow the direct memory transfer controller to steal one memory cycle. The microprocessor will then continue its operation and will allow the DMA data transfer to take place, on the system busses, between the execution of the microprocessor's instructions.
The DMA controller is an interface between the microprocessor, the peripherals and the internal system memory and therefore requires circuits necessary for communication with the microprocessor. In addition, the DMA controller includes an address register, a byte count register, a control register and a set of address lines. The address register and the address lines are used for direct communication with the internal system memory. The byte count register specifies the number of bytes remaining to be transferred by the DMA controller. The control register specifies the direction of the data transfer and other user selectable DMA transfer options. The data transfer is usually done directly between the specific peripheral device and the internal system memory, utilizing the data bus, under the supervision of the DMA controller.
A bus request signal line and a bus granted signal line are coupled between the microprocessor and the DMA controller. The bus request signal line, sometimes referred to as a hold command, is used by the DMA controller to request that the microprocessor disable its busses and allow the DMA controller to utilize them. The bus granted signal line, sometimes referred to as a hold acknowledge, is used to notify the DMA controller that the microprocessor has given up control of the system busses.
When it is necessary to transfer data from a peripheral device to the internal system memory the bus request signal line is raised by the DMA controller to a logical high voltage level. The microprocessor then completes the execution of the present instruction and places its busses, including the read and write signal lines, into a high-impedance state and then raises the bus granted line to a logical high voltage level. As soon as the bus granted, or hold acknowledge signal signal line is raised to a logical high voltage level, the DMA controller can take control of the system bus to communicate directly with the internal system memory. As long as the bus granted signal line is at a logical high voltage level the microprocessor does not have control of the system busses. To signal that the transfer of data is complete, the DMA controller will lower the bus request signal line to a logical low voltage level. The microprocessor will return to its normal operation after the bus request signal line is lowered to a logical low voltage level by lowering the bus granted signal line to a logical low voltage level and enabling its busses. The DMA controller also communicates with an external peripheral device through DMA request and DMA acknowledge signal lines in order to initiate a DMA transfer of data.
As stated above, the DMA controller includes an address register, a byte count register and a control register. The address register is used to specify the desired location of the data transfer within the internal system memory. The address register is incremented after each DMA byte transfer. The byte count register stores the number of bytes remaining to be transferred to or from the internal system memory. This register is decremented after each DMA byte transfer and is internally tested for zero. Once the byte count is equal to zero, the DMA controller lowers the bus request signal line to a logical low voltage level, signalling that the transfer of data is complete. Alternatively, the byte count register can store the number of bytes that have already been transferred. The byte count register will then be initialized to zero and incremented after each DMA byte transfer. In this case, the byte count register is internally compared against the number of total bytes of data to be transferred. The control register specifies the direction of the data transfer, whether it is into (write) or out of (read) the internal system memory. The microprocessor can read from or write into the three registers within the DMA controller.
A data transfer using DMA is first initialized by the microprocessor. The initialization is essentially a program consisting of instructions that include loading the three registers within the DMA controller with the specific information regarding the DMA transfer. During initialization, the address register is loaded with the address within the internal system memory where the transfer is to take place, the byte count register is loaded with the number of bytes to be transferred, the control register is loaded with the information regarding the direction of the data transfer.
After this initialization, a peripheral device can also initiate a DMA transfer by sending the DMA controller a DMA request signal. When the DMA controller receives a DMA request signal from a peripheral device, it activates its bus request signal line, informing the microprocessor that the DMA controller wishes to transfer data. As explained above the microprocessor then completes the execution of the present instruction and places its busses, including the read and write lines, into a high-impedance state. Once the DMA controller has control of the bus system it then places the current value of its address register onto the address bus, initiates the read or write signal and sends a DMA acknowledge signal to the peripheral device. The peripheral device then puts a byte of data on the data bus for a write operation or receives a byte of data from the data bus for a read operation. Thus, the DMA controller controls the read or write operation and supplies the address for the internal system memory. The peripheral device can then communicate with the internal system memory through the data bus for direct transfer between the two units while the microprocessor is disabled.
For each byte of data that is transferred, the DMA controller increments its address register and decrements its byte count register. If the value stored in the byte count register is not at zero, the DMA controller checks the request line from the peripheral. For a high-speed peripheral, the request line is activated as soon as the previous transfer is completed, a second transfer is then initiated and the process continues until the entire block of data is transferred. If the speed of the peripheral is slower, the request signal from the peripheral may come somewhat later. In this case, the DMA controller removes its bus request and allows the microprocessor to continue to execute its program. When the peripheral catches up and requests a transfer, the DMA controller will request the busses from the microprocessor again.
When the byte count register reaches zero, the DMA controller stops any further transfer of data and removes its bus request. The DMA controller indicates to the requesting peripheral the completion of the DMA transfer. The requesting peripheral may then generate an interrupt request to the microprocessor. When the microprocessor responds to the peripheral interrupt, it reads the contents of the byte count register. The zero value of this register indicates that all of the bytes of data were successfully transferred. The microprocessor can read the value stored in the byte count register at any other time as well, in order to check the number of bytes of data that have already been transferred.
SYSTEM BUSSES
System busses are used to allow circuits within a computer system to communicate with other circuits, such as between peripherals connected to the system and the internal system memory, as described above. A system bus consists of multiple signal lines, including address lines, data lines, Read/Write or handshake lines and other control signal lines. The size of a system bus is dependent on the capabilities of the CPU which is used to control the system bus.
Computer manufacturers have typically designed the internal computer system bus structure around the microprocessor that they support. Because each manufacturer supports its own microprocessor, numerous bus structures have been developed and become standards. IBM developed and uses the ISA bus standard for the IBM PC system bus structure, Apple Computer has developed and uses the NUBUS standard for the system bus architecture of some Macintosh computers, Intel has developed and uses the PCI bus standard and VESA (Video Electronics Standard Association) has developed and uses the Local Bus standard (VL Bus). There are many other bus structures used within various electronic equipment, but most of these system busses have not become popular standards because either the equipment is not used widely or the system bus is proprietary and is not disclosed. Not all of these bus structures have the capability to support DMA data transfer.
Of interest herein are the computer system busses developed around X86 family of microprocessors, including the ISA bus and the PCI bus and other processors built around the PCI bus. However, it will become clear that the present invention can be applied to other bus structures as well.
The ISA bus standard is used in almost every IBM PC or PC clone and accordingly has become a very popular bus standard. The ISA bus standard was created by IBM and has a 16 bit wide data path and a 24 bit wide address bus. The ISA bus is asynchronous and commonly operated with system clock rates of 8 MHz. Because the ISA bus standard has remained fixed, it has become limited for use in conjunction with modern high speed microprocessors. However, the ISA bus does have the capability to support DMA data transfers.
The PCI bus standard is a high-performance computer bus that was co-sponsored by Intel Corporation. The PCI bus standard has power saving features as well as a faster bandwidth rate than the ISA bus standard. The PCI bus standard also utilizes a 32 bit wide data/address bus. However, the PCI bus does not have the capability to support DMA data transfers.
The Personal Computer Memory Card International Association (PCMCIA) is an association which sets standards and specifications by which a peripheral communicates to a host adapter or CPU through an interface. A PCMCIA card is used as this standard interface and allows peripheral devices including a modem card, a network card, a sound card, a floppy disk drive and a hard disk drive to be coupled to the system computer through a PCMCIA card. This PCMCIA card is plugged into a PCMCIA expansion slot which is coupled to a PCMCIA adapter within the computer system. The PCMCIA standard enables memory and I/O devices to be inserted as exchangeable peripherals into personal computers.
A block diagram of a computer system which has PCMCIA capability is illustrated in FIG. 1A. A motherboard 102 is coupled to a CPU 110, a PCMCIA host adapter 108, a DMA controller 111, an internal system memory 113, a floppy disk drive 120, a hard disk drive 121 and a graphics controller 122. The system busses 112 couple all of the above listed circuits to the CPU 110. The graphics controller 122 is also coupled to the display 101 and the system busses 112 are also coupled to a keyboard or other I/O device 123. The CPU 110 enables the DMA controller 111 to control the system busses 112 for a DMA transfer between a peripheral and the internal system memory 113. The PCMCIA host adapter 108 is also coupled to the two PCMCIA expansion slots 106, 107 by the PCMCIA bus signal lines 114. As peripherals are added to the system, a PCMCIA card 104 or 105 is plugged into one of the PCMCIA expansion slots 106, 107. When a DMA transfer is requested from a peripheral coupled to the PCMCIA host adapter 108, the PCMCIA adapter 108 requests the DMA controller 111 to initialize and execute the DMA transfer.
At the present time, DMA capability is not required by the PCMCIA specification and standards. However, there are peripherals which can be connected to the system computer through the PCMCIA expansion slots 106, 107 and can be operated using a DMA transfer protocol. There are also system busses, such as the ISA bus, which also support DMA transfers. When a DMA transfer is to take place between a PCMCIA peripheral which has DMA capability and a system using a system bus also having DMA capability, the PCMCIA host adapters 108 of the prior art will effectively pass through the necessary DMA signals from the system bus 112 to the PCMCIA bus 114 as illustrated in FIG. 1B.
One of the PCMCIA cards 104 is coupled to a peripheral which does not have DMA capability. The other PCMCIA card 105 is coupled to a peripheral which does have DMA capability. When a PCMCIA card 104 or 105 is plugged into the PCMCIA expansion slot, the PCMCIA host adapter 108 first interrogates the PCMCIA card 104 or 105 to determine whether or not it has DMA capability. As long as that card remains plugged into the expansion slot 106, the PCMCIA host adapter 108 will know that it does or does not have DMA capability.
What is needed is a PCMCIA Host Adapter which can be coupled to a system bus which does not support DMA transfers and will take over the system bus during data transfers between the system memory and the peripherals plugged into the PCMCIA slots and effectively control a DMA data transfer between the peripheral and the system bus.